The invention relates to a semiconductor device of the hetero-junction transistor type comprising a stack of semiconductor layers which constitute a source region, a gate region and a drain region, while the current path established between the said source and drain regions is substantially at right angles to the various junctions.
Hetero-junction structures are well known from the prior art as designed and tested in the years 1950 ff. However, although they have very interesting potential properties superior to those of homo-junctions, they have been developed to only a small extent, except perhaps in opto-electronic devices, such as lasers. Thus, although numerous books and publications have appeared about semiconductor hetero-junction devices, the main applications developed for the market are of the homo-junction type.
One of the reasons for this slow development of hetero-junction devices resides in the poor crystalline and electrical quality of the layers at the interfaces due to the growing methods utilized thus far, which result in a considerable recombination of the charge carriers at the interfaces.
The novel growing methods developed since then, such as, for example, epitaxy from the vapor phase with the use of organometallic compounds, molecular beam epitaxy and other methods, have reduced to a large extent the aforementioned disadvantages and improved the steepness of the transitions and the freedom of choice of the configurations of the conduction bands.
Consequently, hetero-junction semiconductor devices have become more popular.
A recent example of a patent application for a hetero-junction semiconductor device is the European patent application EP No. 0 027 761 which discloses a horizontal transistor, the gate region of which comprises a P/N hetero junction (GaAsP/Ga.sub.1-x Al.sub.x AsN), in which a charge inversion layer is formed for a positive polarization of the gate region.